FPGA VLSI Projects list 2012 - 2013

1 Low-Power And Area-Efficient Carry Select Adder 


2 Digital Image Authentication From JPEG Headers 


3 Building An AMBA AHB Compliant Memory Controller 


4 A Robust FSM Watermarking Scheme For IP Protection Of Sequential Circuit
Design. 


5 Design Of Sequential Elements For Low Power Clocking System. 


6 Innovative Application Of RFID Systems To Special Education Schools 


7 Field Programmable Gate Array Prototyping Of End-Around Carry Parallel Prefix Tree Architectures. 


8 A New Reversible Design Of BCD Adder 


9 Efficient Pattern Matching Algorithm For Memory Architecture 


10 The Realization Of Precision Agriculture Monitoring System Based On Wireless Sensor Network 


11 Bus Matrix Synthesis Based On Steiner Graphs For Power Efficient System-On-
Chip Communications 


12 New Architectural Design Of CA-Based Codec. 


13 An Autonomous Vectorscalar Floating Point Coprocessor For FPGAs 
14 Adiabatic Technique For Energy Efficient Logic Circuits Design 


15 4 Bit SQF Multiplier Based On Booth Encoder 


16 A Low-Power And Portable Spread Spectrum Clock Generator For SOC
Applications 


17 Period Extension And Randomness Enhancement Using High-Throughput
Reseeding-Mixing Prng. 


18 Mapping Multi-Domain Applications Onto Coarse-Grained Reconfigurable
Architectures 


19 The Communication Interface Design Of AT89C51 


20 Area-Efficient Scalable Map Processor Design For High-Throughput
Multistandard Convolutional Turbo Decoding 


21 A Design Of Network Remote Control System 


22 Efficient Codec Designs For Crosstalk Avoidance Codes Based On Numeral
Systems 


23 Blind Spectrum Sensing For OFDM-Based Cognitive Radio Systems 


24 Design And Characterization Of Parallel Prefix Adders Using FPGAs 


25 Low-Power And Area-Efficient Carry Select Adder 


26 Preparation Robot Based On Serial 


27 Peak Power Analysis Of MC-CDMA Employing Golay Complementary
Sequences 


28 A Distributed Canny Edge Detector And Its Implementation On FPGA 


29 An FPGA-Based Architecture For Linear And Morphological Image Filtering 


30 FPGA Based Real-Time Adaptive Fuzzy Logic Controller 


31 Design Of Low Power And High Speed Configurable Booth Multiplier


32 Dual Stack Method A Novel Approach To Low Leakage And Speed Power
Product Vlsi Design 


33 Mapping Multi-Domain Applications Onto Coarse-Grained Reconfigurable
Architectures. 


34 MasliNET: A Wireless Sensor Network Based Environmental Monitoring System 


35 On Profibus-DP Slave Station Controller Based On NIOS II


36 An Efficient Architecture Design For VGA Monitor Controller 


37 IEEE 1451-Based Multi-Interface Module (I2M) For Industrial Processes
Automation 


38 Design And Implementation Of Cordic Processor For Complex DPLL 


39 High-Accuracy Fixed-Width Modified Booth Multipliers For Lossy Applications 


40 Efficient Iterative Techniques For Soft Decision Decoding Of Reed-Solomon
Codes 


41 Design And Sensitivity Analysis Of A New Current-Mode Sense Amplifier For
Low-Power SRAM 


42 An Implementation Of A 2D FIR Filter Using The Signed-Digit Number System 


43 A Novel Low Power And High Speed Wallace Tree Multiplier For RISC
Processor 


44 Hardware Realization Of Shadow Detection Algorithm In FPGA 


45 Fixed-State Tests For Delay Faults In Scan Designs 


46 Design Of An Error Detection And Data Recovery Architecture For Motion
Estimation Testing Applications. 


47 Image Encryption Based On AES Key Expansion 


48 Digital Watermarking Using Bidimensional Empirical Mode Decomposition 


49 Efficient Weighted Modulo 2N+1 Adders By Partitioned Parallel-Prefix
Computation And Enhanced Circular Carry Generation 


50 An Ultra-Low-Power BPSK Receiver And Demodulator Based On Injection-
Locked Oscillators 


51 High Speed ASIC Design Of Complex Multiplier Using Vedic Mathematics 


52 Fuzzy Random Impulse Noise Removal From Color Image Sequences 


53 A Flexible Hardware Implementation Of SHA-1 And SHA-2 Hash Functions 


54 PVT Variation Tolerant Current Source With On-Chip Digital Self-Calibration 


55 Effect Of Carrier Frequency Offset On Single-Carrier CDMA With Frequency-
Domain Equalization 


56 Implementation Of A Self-Motivated Arbitration Scheme For The Multilayer AHB Bus Matrix. 


57 On The Transmission Method For Short Range MIMO Communications 


58 Enhancing Learning Of Digital Systems Using A Remote FPGA Lab 


59 Operation Improvement Of Indoor Robot By Gesture Recognition 


60 New Approach To Look-Up-Table Design And Memory-Based Realization Of
FIR Digital Filter. 


61 A Low-Power Single-Phase Clock Multiband Flexible Divider. 


62 A Median Filter FPGA With Harvard Architecture 


63 An Efficient 4-D 8PSK TCM Decoder Architecture 


64 A Lightweight High-Performance Fault Detection Scheme For The Advanced
Encryption Standard Using Composite Fields 


65 Performance Analysis Of Integer Wavelet Transform For Image Compression 


66 An Enhanced Canary-Based System With BIST For SRAM Standby Power
Reduction 


67 FPGA Implementation Of RS232 To Universal Serial Bus Converter 


68 Performance Efficient FPGA Implementation Of Parallel 2-D MRI Image Filtering Algorithms Using Xilinx System Generator 


69 Mobile Video Monitoring System Based On FPGA & GPRS 


70 Direct Digital Frequency Synthesizer Using Nonuniform Piecewise-Linear
Approximation 


71 Algorithm Of Binary Image Labeling And Parameter Extracting Based On FPGA 


72 Power Management Of MIMO Network Interfaces On Mobile Systems 


73 An On-Chip Delay Measurement Technique Using Signature Registers For
Small-Delay Defect Detection. 


74 LUT Optimization For Memory-Based Computation. 


75 Detecting Background Setting For Dynamic Scene 


76 Low-Complexity Sequential Searcher For Robust Symbol Synchronization In
OFDM Systems 


77 Recognition FPGA System For Detection Of Anomalies In Mammograms 


78 Low Complexity Digit Serial Systolic Montgomery Multipliers For Special Class Of GF(2M) 


79 High-Accuracy Fixed-Width Modified Booth Multipliers For Lossy Applications 


80 Improved Area-Efficient Weighted Modulo 2N + 1 Adder Design With Simple
Correction Schemes. 


81 High Throughput DA-Based DCT With High Accuracy Error-Compensated Adder Tree 


82 Design And VLSI Implementation Of High-Performance Face-Detection Engine For Mobile Applications 


83 A New Adaptive Weight Algorithm For Salt And Pepper Noise Removal 


84 A Rotation-Based Bist With Self-Feedback Logic To Achieve Complete Fault
Coverage 


85 Power-Aware Design With Various Low-Power Algorithms For An H.264/AVC
Encoder 


86 Low Power Chien Search For BCH Decoder Using RT-Level Power
Management 


87 Design And Implementation Of Area-Optimized AES Based On FPGA 


88 Solid Waste Monitoring And Management Using RFID, GIS And GSM 


89 A Robust Edge Encoding Technique For Energy-Efficient Multi-Cycle
Interconnect 


90 Lossless Implementation Of Daubechies 8-Tap Wavelet Transform 


91 A Probabilistic Estimation Bias Circuit For Fixed-Width Booth Multiplier And Its DCT Applications 


92 Sort Optimization Algorithm Of Median Filtering Based On FPGA 


93 On Reducing Scan Shift Activity At RTL 


94 Design And Implementation Of Low Power Digital FIR Filter Based On Low
Power Multipliers And Adders On Xilinx FPGA 


95 On Reducing Hidden Redundant Memory Accesses For DSP Applications 


96 Automatic Road Extraction Using High Resolution Satellite Images Based On Level Set And Mean Shift Methods 


97 PDE-Based Random-Valued Impulse Noise Removal Based On New Class Of
Controlling Functions 


98 Design Of SHA-1 Algorithm Based On FPGA 


99 Implementation And Performance Analysis Of Seal Encryption On FPGA, GPU And Multi-Core Processors 


100 Design Space Exploration Of Hard-Decision Viterbi Decoding: Algorithm And VLSI Implementation. 


101 A Lightweight High-Performance Fault Detection Scheme For The Advanced
Encryption Standard Using Composite Fields 


102 Accumulator Based 3-Weight Pattern Generation(Testing) 


103 A Secure Field Programmable Gate Array Based System-On-Chip For
Telemedicine Application 


104 A Formal Approach To Designing Cryptographic Processors Based On GF(2^M) Arithmetic Circuits 


105 FPGA Design Of AES Core Architecture For Portable Hard Disk 


106 Design Of A Low Power Flip-Flop Using CMOS Deep Submicron Technology 


107 Removal Of High Density Salt And Pepper Noise Through Modified Decision
Based Unsymmetric Trimmed Median Filter 


108 Design And FPGA Implementation Of Modified Distributive Arithmetic Based DWT-IDWT Processor For Image Compression 


109 FPGA Based FFT Algorithm Implementation In WiMAX Communications System 


110 FPGA Implementation For Humidity And Temperature Remote Sensing System 


111 Face Detection And Recognition Method Based On Skin Color And Depth
Information 


112 Location Cache Design And Performance Analysis For Chip Multiprocessors 


113 Single Cycle Access Structure For Logic Test 


114 Systematic Design Of RSA Processors Based On High-Radix Montgomery
Multipliers 


115 Effective Hybrid Test Program Development For Software-Based Self-Testing Of Pipeline Processor Cores 


116 An FPGA-Based Architecture For Linear And Morphological Image Filtering 


117 Modeling TCP/IP Stack In A Single Custom Processor, With Secure Data
Transmission To An Altera-Based Web Server 


118 Implementing A Safe Embedded Computing System In Sram-Based FPGAs
Using IP Cores: A Case Study Based On The Altera NIOS-II Soft Processor 


119 RFID-Based Hospital Real-Time Patient Management System 


120 A Multibank Memory-Based VLSI Architecture Of DVB Symbol Deinterleaver 


121 Design And Simulation Of UART Serial Communication Module Based On VHDL 


122 Task Migration In Mesh NOCS Over Virtual Point-To-Point Connections 


123 A Review On Power Optimization Of Linear Feedback Shift Register (LFSR) For Low Power Built In Self Test (BIST) 


124 Cyclic Prefixed OQAM-OFDM And Its Application To Single-Carrier FDMA 


125 Embedded Web Server For Remote Laboratory Access For Undergraduate
Students Studying Electronic Engineering 


126 Pseudorandom Bit Generation Using Coupled Congruential Generators. 


127 An Efficient Implementation Of Floating Point Multiplier 


128 High-Speed Low-Power Viterbi Decoder Design For TCM Decoders 


129 A Very Fast And Low Power Carry Select Adder Circuit 


130 Development Of A New Breath Alcohol Detector Without Mouthpiece To Prevent Alcohol-Impaired Driving 


131 The Design Of The Displaying System Based On The SOPC Embedded Chips 


132 High Speed ASIC Design Of Complex Multiplier Using Vedic Mathematics 


133 The Design Of The Emperature And Humidity Supervisory Monitor System 


134 Technique Of LFSR Based Test Generator Synthesis For Deterministic And
Pseudorandom Testing 


135 Ultra Low-Power Clocking Scheme Using Energy Recovery And Clock Gating 


136 Design And Characterization Of Parallel Prefix Adders Using FPGAs 


137 Runtime Resonance Noise Reduction With Current Prediction Enabled
Frequency Actuator 


138 Adaptive OFDM Radar For Target Detection In Multipath Scenarios 


139 A Pipeline VLSI Architecture For High-Speed Computation Of The 1-D Discrete Wavelet Transform


140 A Blind Digital Watermarking Algorithm Based On Wavelet Transform 


141 High-Throughput Interpolator Architecture For Low-Complexity Chase Decoding Of RS Codes. 


142 Image Edge Detection Based On FPGA